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RamFifoVHDL
- Ram Fifo Core VHDL file
fifo89
- 先进先出FIFO缓冲器，8位字宽，9位字深，很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
vhdl
- 该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data re
fifo
- 利用VHDL实现fifo，IPcode 的 FIFO-vhdl for fifo
sfifo
- 牛逼的娴熟的异步fifo，vhdl程序，波形完美-fifo
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
fifo_chipscope
- 学习FIFO的初级资料，代码工程在ISE10.1上运行，还有在线示波器chipscope的步骤指导哦！-Study of the primary data FIFO, the code works ISE10.1 run, there is scope chipscope step online guide Oh!
FIFO
- 这是用VHDL设计的一个8*9阵列的D触发器组成FIFO（first in first out）-This is a VHDL design using an 8* 9 array of D flip-flop composed of FIFO (first in first out)
FIFO24_CS8416[1]
- Fifo buffer vhdl code
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
FIFO
- 用VHDL语言编程实现的FIFO的设计，可用于数据的寄存和缓冲，libero仿真通过-Programming language using the FIFO VHDL design can be used for data storage and buffering, libero simulation by
fifo
- 异步FIFO的VHDL程序，已经通过quartus编译和仿真。 -Asynchronous FIFO, VHDL program, has been compiled by quartus and simulation.
fifo
- fifo in vhdl file code
fifo.vhdl
- 异步fifo的vhdl源代码,可实现异步信号的传送-The asynchronous fifo vhdl source code, enabling the transmission of asynchronous signals
FT245
- 在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
fifo_vhdl
- 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
General-memory-VHDL-code-library
- 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
fifo
- 用vhdl语言实现对八位数据进行缓存的控制-With VHDL language implementation to eight of the data cache of control
Flag-of-asynchronous-FIFO
- Quartus平台，VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.